An integrated circuit is fabricated by translating a circuit design or layout to a semiconductor substrate. In optical lithography, the layout is first transferred onto a physical template, which is in turn, used to optically project the layout onto a silicon wafer. In transferring the layout to a physical template, a mask is generally created for each layer of the integrated circuit design.
The patterned photomask includes transparent and opaque areas for selectively exposing regions of the photoresist-coated wafer to an energy source. To fabricate a particular layer of the design, the corresponding mask is placed over the wafer and light is shone through the mask from the energy source. The end result is a semiconductor wafer coated with a photoresist layer having the desired pattern that defines the geometries, features, lines and shapes of that layer. The photolithography process is typically followed by an etch process during which the underlying substrate not covered or masked by the photoresist pattern is etched away, leaving the desired pattern in the substrate. This process is then repeated for each layer of the design.
Unfortunately, errors may occur during the manufacture of the masks that result in mask defects. A mask defect is any irregularity in the mask that deviates from the mask design. Using a mask having defects during the photolithography process may produce a circuit pattern on the substrate that fails to accurately represent the intended pattern and that may result in a non-functioning circuit, depending on the severity of the defect. A mask defect that will not result in any appreciable error in a circuit if the mask is used during fabrication is considered a “unprintable” defect, while a severe defect that may result in a fatal error in the circuit is deemed “printable”, causing the mask to be discarded.
As semiconductor devices reach submicron feature sizes, the need to analyze the effects of mask defects has become increasingly important. As is well-known in the art, commercial process simulation software is available that makes it possible to predict the structure of a semiconductor device before actual silicon is available. Examples of process simulation software include TSUPREM-4™ and Taurus-LRC™ by Synopsys, Inc. of Mountain View, Calif. TSUPREM-4 is a 1D/2D process-simulation tool for optimizing IC fabrication processes, and Taurus-LRC is a “lithography rule checker” that verifies that a final mask layout delivers the intended result on silicon. Taurus-LRC also generates the expected silicon layout, which is compared to the intended chip layout. Differences larger than user-defined tolerances are reported as errors.
Process simulation software has also been used in automated inspection systems to detect photomask defects. An example of such a system is disclosed in US Patent Application Publication 2002/0019729 by Chang entitled “Visual Inspection And Verification System,” published Feb. 14, 2002. In this system, an image of a defect portion of a mask and a set of lithography parameters are input to an image simulator. The image simulator generates a simulated image in response to the defect area image and the set of lithography parameters. The simulated image is a simulation of an image that would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask. Chang also discloses generating a second simulated image that is a simulation of the wafer print of the portion of the design mask that corresponds to the portion represented by the defect area image. The first and second simulated images are then compared in order to determine the printability of any identified potential defects on the photolithography mask. A method of determining the process window effect of any identified potential defects is also provided for.
Although the defect detection systems described above are an improvement over visual inspection systems, current methods for detecting mask defects have disadvantages. One disadvantage is related to what is used as the input for the process simulation software. In Chang's system, for example, the mask is scanned with a high-resolution microscope or scanning electron microscope (SEM) and images of areas of the mask around identified potential defects are captured as an image. A digitizing device, such as a frame image grabber, is then used to digitize the data. The process simulation software accepts the digitized data and produces the simulation of a stepper image on a wafer for the physical mask. Chang, however, fails to describe how the features of the mask are extracted from the image. Furthermore, process simulation software typically requires the input data to be in GDSII format, and Chang fails to describe that the digitized data is converted to GDSII format. If the photograph of the mask is not accurately converted, then the input to the image simulation software will be inaccurate, and so will the resulting simulation.
Another problem with current defect detection systems is that although current detection systems can find mask defects, each defect is analyzed for its effect only on the horizontal processing layer on which the defect is located. For example, the conventional approach to analyzing a defect is to generate a simulated image from an image of a physical mask, and compare it with a second simulated image that was produced using the design data of the same mask as input (i.e., a mask that is free from defects). Any differences found are deemed defects and are evaluated for acceptance. Thus, the defects are evaluated to determine the impact the defect will have on the current layer in the circuit, which is known as testing for horizontal or spatial defects. However, as those with ordinary skill in the art will appreciate, mask defects may produce defects that affect adjacent layers in the circuit. Current defect detection systems fail to test for such “vertical effects.”
Accordingly, what is needed is a defect detection system that accurately produces input for a simulation image from a photograph of a physical mask, and that analyzes the printability of the defects in the current horizontal layer as well as the vertically adjacent layers in the circuit design. The present invention addresses such a need.